The term graphics processing unit, (GPU) is often utilized to describe circuit cards that can be added to a host computer to upgrade the quality of the graphics displayed to the user. Such expandable systems are becoming more popular due to emergence of visually superior games, medical imaging advancements and also for general purpose computing. These compelling applications have created a need for computing systems with graphics upgrade capabilities or graphics expansion capability. Thus, newer systems provide connections that allow for additional GPU cards to be “plugged in” when increased graphics processing capabilities are desired.
Many GPU's utilize a Peripheral Component Interconnect express (PCIe) compatible components to interconnect the GPU engines or GPU cores. A PCIe bus is an input output (I/O) interconnect bus standard which includes both a protocol and a layered communication architecture that expands on and doubles the data transfer rates of the original Peripheral Component Interconnect (PCI) architecture. PCIe is a two-way, serial connection that carries data in packets along two pairs of point-to-point data lanes, compared to the single parallel data bus of traditional PCI that routes data at a set rate.
Initial bit rates for PCIe busses can reach 2.5 Gb/s per lane direction, which equate to data transfer rates of approximately 500 MB/s. The PCIe specification was developed so that high-speed interconnects such as the Institute of Electrical and Electronic Engineers (IEEE) standard 1394b, uniform serial bus 2.0, “InfiniBand” and “Gigabit Ethernet” can have an I/O architecture suitable for their transfer high speeds. The PCIe format is compatible with legacy PCI systems. PCIe based communications utilize a physical layer that includes a network of serial interconnects. A hub on a main board can act as a crossover switch that allows point-to-point device interconnections to be rerouted “on the fly” to adapt to changing conditions. PCIe is a layered protocol, consisting of a Transaction Layer, a Data Link Layer, and a Physical Layer. The Physical Layer is further divided into a logical sublayer and an electrical sublayer. The logical sublayer is frequently further divided into a Physical Coding Sublayer (PCS) and a Media Access Control (MAC) sublayer.
Multiple GPUs can work collectively as one entity and can share a graphics processing work load even though they may or may not be recognized as separate resources by the host system. PCIe switches can be utilized to interconnect the outputs of GPUs. Thus, a graphics processing task can be segmented into multiple segments and one GPU can process each segment. In this distributed processing architecture/operation it is important to detect, connect and coordinate the multiple GPU's. This coordination can be achieved by a communication bus that connects the GPU's. Such a bus is typically not directly connected to the main or host processor and the host processor typically does not get involved in the graphics rendering process (es) conducted by and between the GPU's.
In fact many different kinds of GPU's exist and are available on the market and communication between such GPUs can pose problems. One such GPU is a Nvidia G80 manufactured by the Nvidia Corporation. The Nvidia G80 utilizes a communication bus referred to as a scalable link interface (SLI). The SLI can link multiple GPUs in a computer system such that the multiple GPU's can share the processing work load. Because a host computer cannot track interactions between the GPU's phenomena can occur where the GPU's will cease functioning properly and the host processor cannot recognize such a phenomena. Current graphics processing systems are less than perfect.